The present invention relates to a semiconductor design technology, and more particularly, to an integrated circuit for compensating for abnormal pull-up and pull-down operations based on external environment and process variations. The present invention may be applied to circuits using an inverter delay having a large skew variation.
In general, when a circuit having Metal-Oxide Semiconductor (MOS) transistors is designed, a skew may occur in a change of a threshold voltage, an oxide thickness, a gate and an active resistance. However, it is difficult to verify the external environment and process variations.
Simulation conditions including ‘FF, FT, FS, TF, TT, TS, SF, ST and SS’ are used to test the external environment and process. ‘FF’ denotes a skew simulation under an NMOS of a fast condition and a PMOS of a fast condition, ‘FT’ denotes a skew simulation under an NMOS of a fast condition and a PMOS of a typical condition, ‘FS’ denotes a skew simulation under an NMOS of a fast condition and a PMOS of a slow condition, ‘TF’ denotes a skew simulation under an NMOS of a typical condition and a PMOS of a fast condition, ‘TT’ denotes a skew simulation under an NMOS of a typical condition and a PMOS of a typical condition, ‘TS’ denotes a skew simulation under an NMOS of a typical condition and a PMOS of a slow condition, ‘SF’ denotes a skew simulation under an NMOS of a slow condition and a PMOS of a fast condition, ‘ST’ denotes a skew simulation under an NMOS of a slow condition and a PMOS of a typical condition, and ‘SS’ denotes a skew simulation under an NMOS of a slow condition and a PMOS of a slow condition,
FIG. 1 is a circuit diagram illustrating a conventional pulse generator and FIG. 2 is a waveform diagram illustrating abnormal pulse signals. The conventional pulse generator includes a delay unit 10, a NAND gate NA1 and first and second inverters INV1 and INV2. The conventional pulse generator generates an output signal OUT through the delay unit 10, the NAND gate NA1 and inverters INV1 and INV2.
The delay unit 10 delays a first input signal IN1 for a predetermined time and outputs a delayed input signal IN1_DLY. The first inverter INV1 inverts a second input signal IN2 and outputs an inverted input signal IN2B. The NAND gate NA1 performs a logical NAND operation of the delayed input signal IN1_DLY and the inverted input signal IN2B. The second inverter INV2 inverts an output signal of the NAND gate NA1 and generates the output signal OUT.
However, when pull-up and pull-down operations are performed in accordance with simulation conditions described above, abnormal operation may occur in the conventional pulse generator as shown in FIG. 1.
That is, as shown in FIG. 2, if the simulation is performed under the typical condition, the rising and falling edges of an output pulse are outputted to have a normal skew as designated by SIGNAL1. However, if the simulation is performed under a slow condition, first and second abnormal signals SIGNAL2 and SIGNAL3 are generated because of a short timing margin between the inverted input signal IN2B and the delayed input signal IN1_DLY delayed by a change of a threshold voltage, an oxide thickness, a gate and an active resistance of NMOS or PMOS transistors included in the delay unit 10.
The first abnormal signal SIGNAL2 is generated when the pull-up MOS transistor is abnormal and the skew of the rising edge of the pulse is abnormal. The second abnormal signal SIGNAL3 is generated when the pull-down MOS transistor of the delay unit is abnormal and the skew of the falling edge of the pulse is abnormal.
Because it is difficult to predict external environment and process variables for circuit malfunctions caused by the pull-up or pull-down variation, it has a problem that the revision is difficult.
Under identical conditions, the pull-up transistor of the delay unit may perform abnormal operations, and the pull-down transistor may perform normal operations.
Moreover, if the change of the pull-up and pull-down is large, a revision process for compensating the operation of pull-up and pull-down elements should be added. This may cause time and cost waste.